1. Technical Field
The present invention relates to a semiconductor device including an electrostatic discharge (ESD) protection circuit for preventing breakdown of the semiconductor device caused by ESD.
2. Background Art
Breakdown due to noise such as electrostatic discharge (ESD) (hereinafter, referred to as ESD) can be named as an important matter to be concerned in ensuring reliability of ICs. Since ESD is an event that possibly occurs in various situations, it is necessary to take measures so as to avoid breakdown of ICs due to the noise.
In semiconductor devices such as ICs, ESD phenomena are classified into several models according to charged objects and discharge forms. Typical models include a human body model (HBM) in which static electricity accumulated in a charged human body discharges to a semiconductor device, a machine model (MM) in which an object having high capacity and low resistance, such as a metal apparatus processing a semiconductor device in a manufacturing process for IC, is assumed to be a generation source of static electricity, a charged device model (CDM) in which a semiconductor device itself is assumed to be charged to perform discharge to others, and the like.
In order to ensure reliability of the semiconductor devices such as ICs, it is necessary to perform simulated ESD on the basis of those discharge models, and to evaluate presence of sufficient immunity.
In an IC, in order to prevent the breakdown due to ESD as described above, various technologies have been conventionally developed and an ESD protection circuit is provided in the IC.
As a conventional ESD protection circuit, a structure illustrated in FIG. 8 is exemplified (for example, JP 11-68043 A). An n+ diffusion layer 201 which becomes a drain of a MOS transistor on a p-type substrate 204 is divided into at least two diffusion regions to be formed in an n-well diffusion layer 203 having the same type. At least one or more p+ diffusion layers 202 having a different type are formed in the n-well diffusion layer 203. The p+ diffusion layer 202 is connected to a substrate potential. In this method, owing not only to a diode formed by a junction between the n-well diffusion layer 203 and the p-type substrate 204 but also to a diode including the n-well diffusion layer 203 and the p+ diffusion layer 202 formed in the n-well diffusion layer 203, a high protection effect can be obtained against ESD irrespective of an application mode of ESD.
Through the progress of miniaturization technologies in the manufacture of a semiconductor device, a reduction of a chip size is accelerated and an internal circuit is made smaller. In the semiconductor device, however, demands for high immunity to ESD never stop in the market to protect the semiconductor device from ESD destruction. The semiconductor device has thus come to a stage in which uniform reduction of a size of the ESD protection circuit similar to the internal circuit is impossible. As a result, the proportion of the ESD protection circuit occupying the chip area becomes larger, and a problem of restriction occurs from the size of the ESD protection circuit even in a plan for lowering manufacturing costs by reducing the chip size.
Besides, the conventional ESD protection circuit may have sufficient immunity in the test method based on the conventional models such as HBM, MM, and CDM. In recent years, however, it has been required to obtain sufficient immunity also with respect to models referred to as an aerial discharge test and a contact discharge test stricter than the conventional models, and thus sufficient immunity cannot be obtained with the use of the conventional ESD protection circuit.
Eventually, since it is necessary to make the size of the ESD protection circuit itself lager, a reducing tendency significantly appears in cost advantage along the chip size reduction by the miniaturization technologies.